UT Electical Engineering and Computer Science : Welcome to the University of Toledo Department of Electrical Engineering and Computer Science.

Dr. Mohammed Niamat

Professor

Contacts

EECS Department
Mail Stop 308
University of Toledo,
Toledo, OH 43606.

Recent Courses

• Field Programmable Logic Devices
• Logic Circuits
• Advanced Digital Circuits
• Digital Systems Design
• Microcomputer Architecture
• Electronics 1 and 2
• Electric Circuits
• Advanced Programming and Algorithms
• Assembly Language Programming
• Systolic Arrays
• Advanced Field Programmable Gate Arrays
• Testing of Digital/VLSI Circuits

Research Interests

• High performance reconfigurable computing and processors including field programmable gate arrays
• Testing of digital, reconfigurable, system on chip (SOC) and VLSI circuits
• Built in self test (BIST)
• Fault modeling
• Modeling and testing of nano electronic devices using quantum dot cellular automata (QCA)
• Parallel processing
• Systolic array architectures and hardware implementation of algorithms

Current Students

• M.S. : Sowmya Panuganti, Barathkumar Vasudevan and Lahari Chalasani

Biography

Dr. Niamat was born in Agra, India. His school education was done at Saint Peters College, Agra. He obtained his Bachelors and Master’s degrees in Electrical Engineering from the Aligarh Muslim University in India. He also obtained a Master’s degree in electrical Engineering from the University of Saskatchewan, Canada, and the PhD degree (1989) from the Dept. of Electrical Engineering, University of Toledo. Dr. Niamat was a Visiting Associate Professor (1996-1997) at Stanford University. He was attached to the Center for Reliable Computing (CRC) where he worked with Prof. Edward J. McCluskey in the area of testing. Before coming to North America, Dr. Niamat worked as an engineer with the U.P. State Electricity Board in India.

Awards and Honors

• Senator, University Faculty Senate, University of Toledo, 2003-2006; 2008-2011.
• Technical Program Committee Member, VLSI Group, IEEE International Symposium on Circuits and Systems (ISCAS), 1996-Continuing. Also, member of the Review Committee

Selected Publications

• M.Y. Niamat, Dileep Koleti, M. Alam , " Testing of LUT Delay Aliasing Faults in SRAM Based FPGAs Using Half Frequencies", IEEE International Midwest Symposium on Circuits and Systems, Montreal, Canada, August 5 -8, 2007.
• M.Y. Niamat, Arunjit Sahni, M. Jamali, "A Built In Self Test Scheme for Automatic Interconnect Fault Diagnosis in Multiple and Single FPGA Systems", IEEE International Midwest Symposium on Circuits and Systems, Montreal, Canada, August 5 -8, 2007.
• M.Y. Niamat, Sarnath Santhanam, J. Kim, "JHDL Implementation of a BIST Scheme for Testing Carry Circuit Multiplexers of SRAM based FPGAs", Fifteenth ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA2007), Monterey, California, Feb. 18 - 20, 2007
• M.Y. Niamat, Dinesh Nemade, M.M. Jamali, "Testing Embedded RAM Modules in SRAM-Based FPGAs", 2006 Fourteenth ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA2006), Monterey, California, Feb. 22-24, 2006.
• M.Y. Niamat, Surya Hejeebu, M. Alam, "A BIST Approach for Testing FPGAs Using JBits", Proc. 2005 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 05), Napa, California, April 17-20, 2005, pp. 267-68.
• M.Y. Niamat, K. Attravanam, M. Alam, "Testing FPGAs Using JBits RTP Cores". IEEE International Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, August 7-10.
• A. Elkammer, S. Vemuru, N. Scheinberg, M. Niamat, "Layout Issues in BUS Encoding Schemes", IEEE International Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, August 7-10.
• M.M. Brown, M.M. Jamali et al, M. Niamat, "A CAN-Based Real-Time Embedded System for DC Motor Control", Published in SAE 2002 Transactions-Journal of Passenger Cars: Electronic and Electrical Systems, pp. 233-239
• M. Y. Niamat and R.R. Jogu, "BIST for a Multiple FPGA System", Proceedings of the 45th IEEE Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma, Aug. 4-7, 2002.
• M.Y. Niamat, Rajesh Nambiar, and M.M. Jamali., "A BIST Scheme for Testing the Interconnects of SRAM-based FPGAs", Proceedings of the 45th IEEE Midwest Symposium on Circuits and Systems, Tulsa, Oklahoma, Aug. 4-7, 2002.